The present invention is directed to data processing systems and, more particularly, to a method and apparatus for obtaining data from a data circuit which has a selected delay between the time a clock signal initiates functioning of the circuit and the time the data apt,ears at an output node of the circuit.
A random access memory is an example of a data circuit which has a selected delay between the time a data clock signal initiates functioning of the circuit and the time the data appears at an output node of the circuit. The delay is usually caused by propagating the data clock signal through a plurality of levels of post-charge inverter logic within the memory circuit. An example of a circuit which employs post-charge logic is disclosed in U.S. Pat. No. 4,985,643, issued to the present inventor and incorporated herein by reference.
To maximize the amount of data that may be obtained from a memory circuit in a given time interval, many applications request new data from the memory circuit before data from a previous request becomes available (i.e., by pipelining data requests). FIG. 1 is a timing diagram illustrating the technique. Assume there is a 20 ns delay between the time a data clock pulse is applied to an input node of a memory circuit and the time the requested data appears at an output node of the circuit. Master clock pulses having a 20 ns period are used to control the memory accesses. A data clock pulse is applied to the input terminal of the circuit at each leading (data clock 1) and trailing (data clock 2) master clock pulse edge for requesting data from the circuit, and the requested data appears at the output node of the circuit 20 ns after each data clock pulse. The data is read at subsequent leading and trailing master clock pulse edges. For example, the data requested at the leading edge of the first master clock pulse (via the first data clock pulse) appears at the output node of the circuit 20 ns later and may be read at the leading edge of the second master clock pulse. Similarly, the data requested at the trailing edge of first master clock pulse (via the second data clock pulse) appears at the output node of the circuit 20 ns later arid may be read at the trailing edge of the second master clock pulse.
While this scheme works as long as the master clock pulses are generated exactly at the frequency determined by the delay of the memory circuit, problems arise when the same scheme is employed with a master clock having a lower frequency or when the propagation delay is less than anticipated due to the memory circuit fabrication tolerances. FIG. 2 is timing diagram of a circuit wherein the master clock pulses have a period of 60 ns. A first data clock pulse is applied to the circuit at the leading edge of the first master clock pulse, and the data appears at the output node of the circuit 20 ns later. A second data clock pulse is applied to the circuit at the trailing edge of the first master clock pulse, and the data appears at the output node of the circuit 20 ns later. At the leading edge of the second master clock pulse, the system attempts to read the data corresponding to the first data clock pulse. Unfortunately, the data corresponding to the second data clock pulse already appeared at the output node of the circuit and overwrote the data corresponding to the first data clock pulse.